1. Field of the Invention
The present invention generally relates to the structure and manufacturing of metal-oxide semiconductor field effect transistors (MOSFETs), and more particularly to MOSFETs manufactured for reproducibility of threshold voltages among otherwise identical transistors.
2. Prior Art
As dimensions of metal-oxide semiconductor (MOS) field effect transistors (FETs) become smaller, they are more and more subject to variations in their properties arising from the randomness of the exact positions of dopants in and near the channel. Such variations, particularly random variations in threshold voltage (σVT), are devastating in circuits like low-power static random access memories. Random variations in threshold voltage increase both the minimum voltage required for reliable operation and the leakage current. Both effects have an adverse effect on the power consumption at a given level of performance.
Random threshold variations σVT are caused by some dominant factors: (i) random dopant fluctuations (RDF) in the well and in the pocket implant regions underneath the gate, which, among other things, cause variations in depletion layer thickness; (ii) line edge roughness (LER) which causes random variation in the length of the gate electrode resulting from random variations in profile of the etched gate; and, (iii) metal gate granularity (MGG) which causes random variations in the local work function due to the grain structure of the gate material. A fourth source of variation is randomness in the effective channel length, arising from statistical variations in the position of the junction that separates the channel from either the source or the drain extensions. This effect, which will be addressed below, has two principal sources: a) variations in the final position of implanted ions due to scattering; and, b) variations in the activation and positions of the source/drain extension ions as influenced by the activation and subsequent heat treatments. Randomness in channel length affects all transistors, but some of the strategies used to mitigate random channel doping fluctuations RDF actually exacerbate the randomness of the channel length.
Drain extensions in modern transistors are required because the very heavily doped sources and drains, if they were located immediately adjacent to the channel region, would out-diffuse into the channel and cause short circuits at the worst or very high leakage at the least. The drain extensions, even though fairly heavily doped for conductivity, allow the heaviest implants to be positioned some distance from the channel.
FIGS. 1A through 1D show a typical approach to creating drain and source extensions. FIG. 1A shows a cross-section of a substrate with well implants 110, and that has a gate oxide 120 grown on it. Over the gate oxide there is a silicon gate 130, either polycrystalline or amorphous, and that gate has been oxidized to form an oxidation layer 140 subsequent to patterning. At this stage, FIG. 1B, an ion implantation or a sequence of implantations 151 are used to create source and drain extensions 150.
FIG. 1C shows a spacer 160 that has been formed by chemical vapor deposition (CVD), with or without plasma assistance, of silicon nitride typically. Through the use of anisotropic plasma etching, the deposited material, e. g., nitride, is removed from all surfaces parallel to the silicon wafer surface, but the spacer 160 remains on the sidewall. The spacer protects the source and drain extensions 150 during the ion implantation 171 that creates the very heavily doped source and drain regions 170. The ion implantation steps 151 and 171 must be followed by an annealing step to repair crystal damage and to activate the dopants. While at least one annealing step is required, some process flows anneal multiple times. In a complementary metal oxide semiconductor (CMOS) process, the implant steps 151 and 171 must be done for both n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) devices. Rapid thermal annealing is the norm for implants 351 and 371, but peak temperatures can exceed 1000° C. As suggested by FIG. 1D, the sheet resistance of the source and drain regions 170 is further reduced by reaction with metallic Ti, Co or Ni to form a highly conductive layer of metal silicide 180. These steps are followed by the formation of interlayer dielectrics (ILD), contacts, and multiple layers of interconnect.
Even though the gate 130 and its oxide 140 act as a hard mask, the final locations of the channel defining edges of the source and drain extensions 150 are subject to localized, random variations. Some of these variations are associated with scattering of the implanted ions as they come to rest in the silicon, and some of the variations are associated with local diffusion of both the doping ions and crystalline defects during the annealing processes. The overall effect of these uncertainties is to impose a random variation on the length of the channel. For transistors having channel lengths of less than 65 nm, the channel length affects both the threshold voltage and the current carrying capability of the transistors. Some of these effects are mitigated by adding pocket implants to the drain extension sequence 151, but the pocket implants are also subject to random variations.
Certain approaches to reducing the effect of random doping density variations involve the use of a very lightly doped epitaxial layer beneath the gate. This class of transistor, which will be referred to herein as an epitaxial transistor, has been described variously in past publications including M. Aoki, et al., “0.1 mu m CMOS devices using low-impurity-channel transistors (LICT),” Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International, pp. 939, 941, 9-12 Dec. 1990. More recent publications include Asenov et al. in the paper “Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-μm MOSFETs with Epitaxial and δ-Doped Channels,” IEEE Transactions on Electron Devices, Vol. 46, No. 8, August 1999, Pages 1718-1724, Fujita et al. in their paper “Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications”, Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 32.3.1-32.3.4, 5-7 Dec. 2011, Clark, et al., “A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits,”, Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 14.4.1-14.4.4, 10-13 Dec. 2011, and U.S. Pat. No. 8,273,617 B2, “Electronic devices and systems,) and methods for making and using the same,” by Thompson and Thummalapally (Sep. 25, 2012). The very lightly doped channel regions are more subject to threshold perturbations by the tails of source/drain extension implants.
In view of the deficiencies of the prior art it would be advantageous to provide a transistor structure and/or a manufacturing process that reduces variations between otherwise identical transistors of an integrated circuit.